1. Field of the Invention
The present invention relates generally to semiconductor memory devices and a data transferring method therein, and more particularly, to a semiconductor memory device having a hierarchical organization in which a plurality of bit line pairs are connected to a sub-input/output line pair through transfer gates and a register for storing data is connected to the sub-input/output line pair and a method for transferring data from the register to memory cells.
2. Description of the Background Art
FIG. 1 is a partial circuit diagram showing a structure of a conventional two-port memory device, showing a portion corresponding to a pair of bit lines. In FIG. 1, this two-port memory device comprises a random access memory (RAM) portion and a serial access memory (SAM) portion. The two memory portions are connected to each other by transfer gates 1. On-off control of the transfer gates 1 is performed in response to a transfer gate control signal TG. The SAM portion comprises a register 2 having a latching function. The RAM portion comprises a sense amplifier 3, a bit line pair BL and BL, word lines WL.sub.1, WL.sub.2, . . . , memory cells MC each having a transfer gate 4 for memory cell and a capacitor 5 for memory cell, and bit line precharging transistors 6. The sense amplifier 3 is activated by sense amplifier activating signals SAE and SAE, to amplify and detect a very small potential difference between the bit line pair BL and BL. On-off control of each of the transfer gates 4 is controlled by selecting or non-selecting a corresponding word line. Each of the bit line precharging transistors 6 is turned on when a bit line precharging signal BLP is activated, to precharge the bit line pair BL and BL at a precharge voltage V.sub.BL.
Referring now to a timing chart of FIG. 2, description is made on an operation for transferring and writing data to memory cells from the register 2 shown in FIG. 1.
First, at the time t1, the transfer gate control signal TG becomes the "H" level, so that the transfer gates 1 are turned on. Consequently, data stored in the register 2 is transmitted to the bit line pair BL and BL through the transfer gates 1. On this occasion, in the RAM portion, when the bit line pair BL and BL is being precharged, the data stored in the register 2 is destroyed. Thus, the transfer gate control signal TG is adapted to be the "H" level after the bit line precharging signal BLP becomes the "L" level so that the bit line pair BL and BL are electrically isolated from each other.
After the data stored in the register 2 is transmitted to the bit line pair BL and BL, a potential on the word line WL is raised at the time t2, so that the transfer gate 4 is turned on. Thereafter, at the time t3, the sense amplifier activating signals SAE and SAE are respectively brought to the "H" and "L" levels, so that the sense amplifier 3 is activated. Consequently, the data transmitted onto the bit line pair BL and BL, i.e., the data stored in the register 2 is written into the memory cell MC.
In the above described semiconductor memory device in which a single register 2 is connected to each bit line pair through a pair of transfer gates 1, data can be transferred from the register 2 to memory cells MC according to the above described transferring method.
Meanwhile, in the semiconductor memory device shown in FIG. 1, the number of memory cells MC connected to a single bit line pair BL and BL is large, so that parasitic capacitance of each bit line is increased, whereby the number of read errors is increased.
Therefore, it is considered that a single bit line pair is divided into a plurality of bit line pairs, each of the divided bit line pairs is connected to a single sub-input/output line pair through transfer gates, and data is transferred to or from a data register through this sub-input/output line pair, so that parasitic capacitance of each of the bit line pairs is decreased, whereby the number of read errors is decreased. An example of a semiconductor memory device fabricated based on such an idea is shown in FIG. 3.
In the semiconductor memory device shown in FIG. 3, a single register 2 corresponds to two bit line pairs BL.sub.1 and BL.sub.1 and BL.sub.2 and BL.sub.2 (a single register may correspond to three or more bit line pairs). Sense amplifiers 3.sub.1 and 3.sub.2 are respectively connected to the bit line pairs BL.sub.1 and BL.sub.1 and BL.sub.2 and BL.sub.2 . The sense amplifiers 3.sub.1 and 3.sub.2 are activated by common sense amplifier activating signals SAE and SAE. In addition, the bit line pair BL.sub.1 and BL.sub.1 is connected to a sub-input/output line pair sub-I/O and sub.-I/O through a transfer gate 7.sub.1, and the bit line pair BL.sub.2 and BL.sub.2 is connected to a sub-input/output line pair sub.-I/O and sub.-I/O through a transfer gate 7.sub.2. The sub-input/output line pair sub.-I/O and sub.-I/O is connected to the register 2 through transfer gates 1. The register 2 is connected to an input/output line pair I/O and I/O through I/O transfer gates 8. On-off control of the I/O transfer gates 8 is controlled by an output signal Yi from a column decoder (not shown).
The above described semiconductor memory device shown in FIG. 3 is adapted such that the transfer gates 7.sub.1 and 7.sub.2 are selectively turned on in response to sense amplifier connect signals SAC1 and SAC2, so that one of the two bit line pairs is connected to the sub-input/output line pair sub.-I/O and sub.-I/O, whereby data stored in the register 2 is transferred to a memory cell connected to one bit line of a desired bit line pair.
Meanwhile, in the semiconductor memory device shown in FIG. 3, if and when data is transferred from the register 2 to a memory cell connected to one of the plurality of bit line pairs BL.sub.1 and BL.sub.1 and BL.sub.2 and BL.sub.2 , data stored in a memory cell connected to bit lines of a non-selected bit line pair, i.e., a bit line pair to which data is not transferred is liable to be destroyed, that is, data opposite to the stored data is liable to be stored. When transient occurs on the bit line BL.sub.1, it is coupled onto SAE and SAE lines by the sense amplifier 3.sub.1 of thence to the sense amplifier 3.sub.2. If large enough to activate the sense amplifier 3.sub.2 during unbalanced capacitive coupling of BL.sub.1 +BL.sub.2, data is destroyed. This will be described with reference to a timing chart of FIG. 4.
As an example, let us consider a case in which the data stored in the register 2 is transferred to a memory cell MC.sub.11 connected to the bit line BL.sub.1 of the bit line pair BL.sub.1 and BL.sub.1 and selected by a word line WL.sub.1. Meanwhile, in the initial state, it is assumed that the sub-input/output lines sub.-I/O and sub.-I/O are respectively brought to the "H" and "L" levels depending on the data stored in the register 2, and "L" level data are stored in memory cells MC.sub.11 and MC.sub.12 respectively connected to the bit lines BL.sub.1 and BL.sub.1 out of memory cells selected by the word line WL.sub.1, as well as in memory cells MC.sub.21 and MC.sub.22 respectively connected to the bit lines BL.sub.2 and BL.sub.2 .
First, when a column address strobe signal CAS falls at the time t1, the sense amplifier connect signal SAC1 rises at the time t2 in order to connect the sub-input/output line pair sub.-I/O and sub.-I/O to the bit line pair BL.sub.1 and BL.sub.1 . Consequently, a pair of transfer gates 7.sub.1 is turned on, so that the data stored in the register 2 is transferred to the bit line pair BL.sub.1 and BL.sub.1 . Meanwhile, since a bit line pair connected to the sub-input/output line pair sub.-I/O and sub.-I/O is selected based on information stored in a column address for selecting a bit line pair, the sense amplifier connect signal SAC1 corresponding to the bit line pair BL.sub.1 and BL.sub.1 to be selected after the column address strobe signal CAS rises.
Thereafter, at the time t3, a potential on the word line WL.sub.1 rises, so that the data stored in the memory cells MC.sub.11 and MC.sub.21 connected to the word line WL.sub.1 are read out onto the bit line pair BL.sub.1 and BL.sub.2. In this case, since current driving capability based on the register 2 is larger than that based on the data stored in the memory cell MC.sub.11, the data stored in the register 2 is maintained. Meanwhile, in order to shorten a period during which a bit line pair is electrically floating (that is, to shorten a period from t3 to t4 which elapses until a sensing operation is initiated) after the potential on the word line WL.sub.1 is raised, the potential on the word line WL.sub.1 is raised after the sense amplifier connect signal SAC1 rises. Thereafter, at the time t4, the sense amplifier activating signals SAE and SAE respectively become the "H" and "L" levels. Accordingly, the sense amplifiers 3.sub.1 and 3.sub.2 are activated, which respectively amplify and detect potential differences between the bit line pair BL.sub.1 and BL.sub.1 and BL.sub.2 and BL.sub.2
Meanwhile, when the data stored in the register 2 is transferred to the selected bit line pair BL.sub.1 and BL.sub.1 at the time t2, noises are included in the sense amplifier activating signals SAE and SAE due to capacitive coupling of transistors constituting the sense amplifier 3.sub.1. During a period from t2 to t3, the sense amplifier activating signals SAE and SAE fluctuate due to the noises until the sense amplifier can be activated. The sense amplifier 3.sub.2 is then activated, so that the potential difference between the bit line pair BL.sub.2 and BL.sub.2 is amplified. On this occasion, the data stored in the memory cell MC.sub.21 has not read out onto the bit line BL.sub.2 yet. Thus, the bit line pair BL.sub.2 and BL.sub.2 remain at a precharge voltage V.sub.BL, so that the potential difference therebetween should not exist. However, when there exist imbalance between potentials on bit lines caused by parasitic capacitance of each bit line and the dissymmetry of amplification sensitivity which inherently exists in the sense amplifier 3.sub.2, the sense amplifier 3.sub.2 undesirably amplifies the potential difference between the bit line pair BL.sub.2 and BL.sub.2 . If the potential difference between the bit line pair BL.sub.2 and BL.sub.2 amplified by the sense amplifier 3.sub.2 is contrary to a potential difference based on data read out from the memory cell MC.sub.21 selected by the word line WL.sub.1, the data stored in the selected memory cell is inverted, i.e., destroyed.
As described in the foregoing, in the semiconductor memory device shown in FIG. 3, data in a memory cell belonging to a non-selected bit line pair, i.e., a bit line pair to which data is inhibited from being transferred is undesirably destroyed.